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regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein.
hm62l36256 series 9m synchronous fast static ram (256k-word 36-bit) ade-203-1318a (z) rev.1.0 dec. 14, 2001 description the hm62l36256 is a synchronous fast static ram organized as 256-kword 36-bit. it has realized high speed access time by employing the most advanced cmos process and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. it is packaged in standard 119-bump bga. note: all power supply and ground pins must be connected for proper operation of the device. features ? 2.5v 5% and 3.3v 3% operation ? synchronous register to register operation ? internal self-timed late write ? byte write control (4 byte write selects, one for each 9-bit) ? optional 18 configuration ? hstl compatible i/o ? programmable impedance output drivers ? differential hstl clock inputs ? asynchronous g output control ? asynchronous sleep mode ? fc-bga 119pin package with sram jedec standard pinout ? limited set of boundary scan jtag ieee 1149.1 compatible ordering information type no. organization access time cycle time package hm62l36256bp-28 HM62L36256BP-33 256k 36 256k 36 1.6 ns 1.7 ns 2.85 ns 3.3 ns 119-bump 1.27 mm 14 mm 22 mm bga (bp-119c)
hm62l36256 series 2 pin arrangement 1 2 3 4 5 6 7 a v ddq sa0 sa1 nc sa13 sa12 v ddq b nc nc sa2 nc sa14 sa11 nc c nc sa3 sa4 v dd sa5 sa6 nc d dqc5 dqc0 v ss zq v ss dqb0 dqb5 e dqc4 dqc3 v ss ss v ss dqb3 dqb4 f v ddq dqc1 v ss g v ss dqb1 v ddq g dqc8 dqc6 swec nc sweb dqb6 dqb8 h dqc7 dqc2 v ss nc v ss dqb2 dqb7 j v ddq v dd v ref v dd v ref v dd v ddq k dqd7 dqd2 v ss k v ss dqa2 dqa7 l dqd8 dqd6 swed k swea dqa6 dqa8 m v ddq dqd1 v ss swe v ss dqa1 v ddq n dqd4 dqd3 v ss sa8 v ss dqa3 dqa4 p dqd5 dqd0 v ss sa10 v ss dqa0 dqa5 r nc sa7 m1 v dd m2 sa15 nc t nc nc sa9 sa16 sa17 nc zz u v ddq tms tdi tck tdo nc v ddq (top view)
hm62l36256 series 3 b lock diagram read adr reg. write adr re g . 256k x 36 memory array ss re g . swe reg. output reg. din reg. sa0-17 swe ss 1 0 clk 1 0 sa0-17 compare swex 1st reg. swex (x=a,b,c,d) swex 2nd re g . byte write control output enable match0 impedance control dqxn (x = a, b, c, d, n = 0 ? 8) g zq
hm62l36256 series 4 pin descriptions name i/o type descriptions notes v dd supply core power supply v ss supply ground v ddq supply output power supply v ref supply input reference: provides input reference voltage k input clock input. active high. k input clock input. active low. ss input synchronous chip select swe input synchronous write enable san input synchronous address input n = 0-17 swex input synchronous byte write enables x = a, b, c, d g input asynchronous output enable zz input power down mode select zq input output impedance control 1 dqxn i/o synchronous data input/output x = a, b, c, d n=0, 1, 2 ... 8 m1, m2 input output protocol mode select tms input boundary scan test mode select tck input boundary scan test clock tdi input boundary scan test data input tdo output boundary scan test data output nc ? no connection m1 m2 protocol notes v ss v ddq synchronous register to register operation (late write mode) 2 notes: 1. zq is to be connected to v ss via a resistance rq where 175 ? rq 300 ? . if zq=v ddq or open, output buffer impedance will be maximum. 2. there is 1 protocol with mode pin. for this application, m1 and m2 need to connect to v ss and v dd respectively. the state of the mode control inputs must be set before power-up and must not change during device operation. mode control inputs are not standard inputs and may not meet v ih or v il specification. this sram is tested only in the synchronous register to register operation.
hm62l36256 series 5 truth table zz ss ss ss ss g g g g swe swe swe swe swea swea swea swea sweb sweb sweb sweb swec swec swec swec swed swed swed swed k k k k k operation dq (n) dq (n+1) h x x x x x x x x x sleep mode high-z high-z l h x x x x x x l-h h-l dead (not selected) x high-z l x h h x x x x x x dead (dummy read) high-z x l l l h x x x x l-h h-l read x dout (a, b, c, d) 0-8 l l x l l l l l l-h h-l write a, b, c, d byte high-z din (a, b, c, d) 0-8 l l x l h l l l l-h h-l write b, c, d byte high-z din (b, c, d) 0-8 l l x l l h l l l-h h-l write a, c, d byte high-z din (a, c, d) 0-8 l l x l l l h l l-h h-l write a, b, d byte high-z din (a, b, d) 0-8 l l x l l l l h l-h h-l write a, b, c byte high-z din (a, b, c) 0-8 l l x l h h l l l-h h-l write c, d byte high-z din (c, d) 0-8 l l x l l h h l l-h h-l write a, d byte high-z din (a, d) 0-8 l l x l l l h h l-h h-l write a, b byte high-z din (a, b) 0-8 l l x l h l l h l-h h-l write b, c byte high-z din (b, c) 0-8 l l x l h h h l l-h h-l write d byte high-z din (d) 0-8 l l x l h h l h l-h h-l write c byte high-z din (c) 0-8 l l x l h l h h l-h h-l write b byte high-z din (b) 0-8 l l x l l h h h l-h h-l write a byte high-z din (a) 0-8 notes: 1. x means don?t care for synchronous inputs, and h or l for asynchronous inputs. 2. swe , ss , swea to swed , sa are sampled at the rising edge of k clock. 3. although differential clock operation is implied, this sram will operate properly with one clock phase (either k or k ) tied to v ref . under such single-ended clock operation, all parameters specified within this document will be met.
hm62l36256 series 6 absolute maximum ratings parameter symbol rating unit notes input voltage on any pin v in -0.5 to v ddq + 0.5 v 1, 4 core supply voltage v dd -0.5 to 3.9 v 1 output supply voltage v ddq -0.5 to 2.2 v 1, 4 operating temperature t opr 0 to 70 c storage temperature t stg -55 to 125 c output short-circuit current i out 25 ma latch up current i li 200 ma package junction to case thermal resistance jc 2 c/w 5, 7 package junction to ball thermal resistance jb 5 c/w 6, 7 notes: 1. all voltage is referenced to v ss . 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted the operation conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. these cmos memory circuits have been designed to meet the dc and ac specifications shown in the tables after thermal equilibrium has been established. 4. the following supply voltage application sequence is recommended: v ss , v dd , v ddq , v ref then vin. remember, according to the absolute maximum ratings table, v ddq is not to exceed 2.2v, whatever the instantaneous value of v ddq . 5. jc is measured at the center of mold surface in fluorocarbon. (see figure 1.) 6. jb is measured on the center ball pad after removing the ball in fluorocarbon. (see figure 1.) 7. these thermal resistance values have error of 5c/w. jc jb f i gure 1 . de fi n i t i on o f measurement t.c. fluorocarbon fluorocarbon t.c.
hm62l36256 series 7 note: the following the dc and ac specifications shown in the tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute. recommended dc operating conditions (ta = 0 to 70c) parameter symbol min typ max unit notes power supply voltage -- core v dd 2.38 2.5 2.63 v 2.5 v part 3.2 3.3 3.4 v 3.3 v part power supply voltage -- i/o v ddq 1.4 1.5 1.6 v input reference voltage -- i/o v ref 0.6 0.75 0.9 v 1 input high voltage v ih v ref + 0.1 ? v ddq + 0.3 v 4 input low voltage v il ?0.3 ? v ref ? 0.1 v 4 clock differential voltage v dif 0.1 ? v ddq + 0.3 v 2, 3 clock common mode voltage v cm 0.6 ? 0.90 v 3 notes: 1. peak to peak ac component superimposed on v ref may not exceed 5% of v ref . 2. minimum differential input voltage required for differential input clock operation. 3. see figure 2. 4. v ref = 0.75 v (typ). v dif v cm v ddq v ss figure 2. differential voltage / common mode voltage
hm62l36256 series 8 dc characteristics (ta = 0 to 70c, v dd = 2.5v 5%, 3.3v 3%) parameter symbol min max unit notes input leakage current i li ? 2 a 1 output leakage current i lo ? 5 a 2 standby current i sbzz ? 128 ma 3 v dd operating current, excluding output drivers. i dd ? 550 ma 4 quiescent active power supply current i dd2 ? 200 ma 5 maximum power dissipation, including output drivers p ? 2.3 @ 2.5 v part w 6 ? 2.8 @ 3.3 v part w 6 parameter symbol min typ max unit notes output low voltage v ol v ss ? v ss + 0.4 v 7 output high voltage v oh v ddq ? 0.4 ? v ddq v 8 zq pin connect resistance rq ? 250 ? ? output ?low? current i ol (v ddq /2)/[{(rq/5 ? 5 ? )} -15%] (v ddq /2)/[{(rq/5 ? 5 ? )} +15%] ma 9, 11 output ?high? current i oh (v ddq /2)/[{(rq/5 ? 5 ? )} +15%] (v ddq /2)/[{(rq/5 ? 5 ? )} -15%] ma 10, 11 notes: 1. 0 vin v ddq for all input pins (except v ref , zq, m1, m2 pin) 2. 0 vout v ddq , dq in high?z 3. all inputs (except clock) are held at either v ih or v il , zz is held at v ih , iout = 0 ma. spec is guaranteed at 75 c junction temperature. 4. iout = 0 ma, read 75% / write 25%, v dd = v dd max, frequency = min. cycle 5. iout = 0 ma, read 75% / write 25%, v dd = v dd max, frequency = 3 mhz 6. output drives a 12pf load and switches every cycle. this parameter should be used by the sram designer to determine electrical and package requirements for the sram device 7. i ol = 8 ma minimum impedance output buffer mode 8. i oh = ?8 ma minimum impedance output buffer mode 9. measured at v ol = 1/2 v ddq 10. measured at v oh = 1/2 v ddq 11. output buffer impedance can be programmed by terminating the zq pin to v ss through a precision resister (rq). the value of rq is five times the output impedance desired. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is 250 ? typical. if the status of zq pin is open, output impedance is maximum. maximum impedance occurs with zq connected to v ddq . the impedance update of the output driver occurs when the sram is in high-z. write and deselect operations will synchronously switch the sram into and out of high-z, therefore triggering an update. the user may choose to invoke asynchronous g updates by providing a g setup and hold about the k clock to guarantee the proper update. at power up, the output impedance defaults to minimum impedance. it will take 1024 cycles for the impedance to be completely updated if the programmed impedance is much higher than minimum impedance. the total external capacitance of zq pin must be less than 7.5 pf.
hm62l36256 series 9 ac characteristics (ta = 0 to 70c, v dd = 2.5v 5%, 3.3v 3%) single differential clock register-register mode ?28 ?33 parameter symbol min max min max unit notes ck clock cycle time t khkh 2.85 ? 3.3 ? ns ck clock high width t khkl 1.3 ? 1.3 ? ns ck clock low width t klkh 1.3 ? 1.3 ? ns address setup time t avkh 0.3 ? 0.3 ? ns 2 data setup time t dvkh 0.3 ? 0.3 ? ns 2 address hold time t khax 0.6 ? 0.6 ? ns data hold time t khdx 0.6 ? 0.6 ? ns clock high to output valid t khqv ? 1.6 ? 1.7 ns 1 clock high to output hold t khqx 0.65 ? 0.65 ? ns 1 clock high to output low-z ( ss control) t khqx2 0.65 ? 0.65 ? ns 1, 5 clock high to output high-z t khqz 0.65 2.0 0.65 2.0 ns 1, 3 output enable low to output low-z t glqx 0.1 ? 0.1 ? ns 1, 5 output enable low to output valid t glqv ? 2.0 ? 2.0 ns 1, 3 output enable high to output high-z t ghqz ? 2.0 ? 2.0 ns 1, 3 sleep mode recovery time t zzr 10.0 ? 10.0 ? ns 6 sleep mode enable time t zze ? 9.0 ? 9.0 ns 1, 3, 6 notes: 1. see ac test loading figure. 2. parameter may be guaranteed by design, i.e, without tester guardband. 3. transitions are measured at start point of output high impedance from output low impedance. 4. output driver impedance update specifications for g induced updates. write and deselected cycles will also induce output driver updates during high-z. 5. transitions are measured 50 mv from steady state voltage. 6. when zz is switching, clock input k must be at same logic levels for reliable operation. 7. minimum t khqz and maximum t khqv can not occur at the same time. 8. verified by design and tested without guardband for 3.0 ns speed sort. 9. t khqx min is verified by design and tested without guardband.
hm62l36256 series 10 timing waveforms read cycle-1 read cycle-2 ( ss control) k, k q 1 q 2 ss swe swex dq a2 a3 a4 a1 sa t avkh t khax t avkh t khax t avkh t khax t khqx t khqv k, k a3 a4 a1 sa t avkh t khax t avkh t khax swex ss swe t avkh t khax dq q 0 q 1 q 3 t khqz t khqx2
hm62l36256 series 11 read cycle-3 ( g controlled) q 0 q 1 q 3 a2 a3 a4 a1 sa ss swe swex dq t avkh t khax t avkh t khax t avkh t khax g t ghqz t glqx t glqv
hm62l36256 series 12 write cycle notes: zz = v il , x = a, b, c, d a2 a3 a4 a1 k, k sa ss swe swex dq t avkh t khax t avkh t khax t avkh t khax g d1 d2 d3 d0 t avkh t khax t dvkh t khdx t khk t khk t klk
hm62l36256 series 13 read-write cycle notes: zz = v il , x = a, b, c, d zz control notes: g = v il , x = a, b, c, d when zz is switching, clock input k must be at same logic levels for reliable operation. k, k t khkh t khkl t klkh sa a1 t avkh t khax ss t avkh t khax swex swe t avkh t khax q 1 t zzr dq t zze zz slee p active slee p off slee p active k, k t khkh t khkl t klkh a6 a7 a3 a4 a1 sa t avkh t khax ss t avkh t khax swe t avkh t khax swex t avkh t khax q 0 q 1 d3 q 4 q 6 g t khqv t khqx t ghqz t dvkh t khdx t glqv t glqx t khqz read read ( g control) read write dead ( ss control) write
hm62l36256 series 14 input capacitance (ta=25 c, f= 1 mhz) parameter symbol min max unit pin name input capacitance c in ? 4 pf san, ss , swe , swex clock input capacitance c clk ? 5 pf k, k , g i/o capacitance c io ? 5 pf dqxn note: this parameter is sampled and not 100% tested. ac test conditions parameter symbol conditions unit note input and output timing reference levels v ref 0.75 v input signal amplitude v il , v ih 0.25 to 1.25 v input rise / fall time tr, tf 0.5 (10% to 90%) ns clock input timing reference level differential cross point v dif to clock 0.75 v v cm to clock 0.75 v output loading conditions see figures note: parameters are tested with rq=250 ? and v ddq =1.5v . d q 16.7 ? 16.7 ? 16.7 ? 50 ? 50 ? 50 ? 50 ? 5 p f 5 p f 0.75v 0.75v 0.75v o utput loa di ng con di t i ons
hm62l36256 series 15 boundary scan test access port operations overview in order to perform the interconnect testing of the modules that include this sram, the serial boundary scan test access port (tap) is designed to operate in a manner consistent with ieee standard 1149.1 - 1990. but does not implement all of the functions required for 1149.1 compliance the hm62l series contains a tap controller. instruction register, boundary scans register, bypass register and id register. test access port pins symbol i/o name tck test clock tms test mode select tdi test data in tdo test data out notes: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. to disable the tap, tck must be connected to vss. tdo should be left unconnected. to test boundary scan, zz pin need to be kept below v ref ?0.4 v. tap dc operating characteristics (ta = 0c to 70c) parameter symbol min max notes boundary scan input high voltage v ih 2.0 v 3.6 v boundary scan input low voltage v il ?0.3 v 0.8 v boundary scan input leakage current i li ?2 a +2 a 1 boundary scan output low voltage v ol ? 0.4 v 2 boundary scan output high voltage v oh 2.4 v ? 3 notes: 1. 0 vin v dd for all logic input pin 2. i ol = ?8 ma at v dd = 3.3 v. 3. i oh = 8 ma at v dd = 3.3 v.
hm62l36256 series 16 tap ac operating characteristics (ta = 0c to 70c) parameter symbol min max unit note test clock cycle time t thth 67 ? ns test clock high pulse width t thtl 30 ? ns test clock low pulse width t tlth 30 ? ns test mode select setup t mvth 10 ? ns test mode select hold t thmx 10 ? ns capture setup t cs 10 ? ns 1 capture hold t ch 10 ? ns 1 tdi valid to tck high t dvth 10 ? ns tck high to tdi don?t care t thdx 10 ? ns tck low to tdo unknown t tlqx 0 ? ns tck low to tdo valid t tlqv ? 20 ns note: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture. tap ac test conditions (v dd = 3.3 v) ? temperature 0c ta 70c ? input timing measurement reference level 1.5 v ? input pulse levels 0 to 3.0 v ? input rise/fall time 2.0 ns typical (10% to 90%) ? output timing measurement reference level 1.5 v ? test load termination supply voltage (v t ) 1.5 v ? output load see figures dut tdo z 0 = 50 ? v t 50 ? boundary scan ac test load
hm62l36256 series 17 tap controller timing diagram test access port registers register name length symbol note instruction register 3 bits ir [0;2] bypass register 1 bits bp id register 32 bits id [0;31] boundary scan register 70 bits bs [1;70] tap controller instruction set ir2 ir1 ir0 instruction operation 0 0 0 sample-z tristate all data drivers and capture the pad value 0 0 1 idcode 0 1 0 sample-z tristate all data drivers and capture the pad value 0 1 1 bypass 1 0 0 sample 1 0 1 bypass 1 1 0 bypass 1 1 1 bypass note: this device does not perform extest, intest or the preload portion of the preload command in ieee 1149.1. t thth t thtl t tlth tck t mvth t thmx t dvth t thdx t tlqv t tlqx t cs t ch tms tdi tdo ram address tap controller timing diagram
hm62l36256 series 18 boundary scan order (hm62l36256) bit # bump id signal name bit # bump id signal name 1 5r m2 36 3b sa 2 4p sa 37 2b nc 3 4t sa 38 3a sa 4 6r sa 39 3c sa 5 5t sa 40 2c sa 6 7t zz 41 2a sa 7 6p dqa 42 2d dqc 8 7p dqa 43 1d dqc 9 6n dqa 44 2e dqc 10 7n dqa 45 1e dqc 11 6m dqa 46 2f dqc 12 6l dqa 47 2g dqc 13 7l dqa 48 1g dqc 14 6k dqa 49 2h dqc 15 7k dqa 50 1h dqc 16 5l swea 51 3g swec 17 4l k 52 4d zq 18 4k k 53 4e ss 19 4f g 54 4g nc 20 5g sweb 55 4h nc 21 7h dqb 56 4m swe 22 6h dqb 57 3l swed 23 7g dqb 58 1k dqd 24 6g dqb 59 2k dqd 25 6f dqb 60 1l dqd 26 7e dqb 61 2l dqd 27 6e dqb 62 2m dqd 28 7d dqb 63 1n dqd 29 6d dqb 64 2n dqd 30 6a sa 65 1p dqd 31 6c sa 66 2p dqd 32 5c sa 67 3t sa 33 5a sa 68 2r sa 34 6b sa 69 4n sa 35 5b sa 70 3r m1 notes: 1. bit#1 is the first scan bit to exit the chip. 2. the nc pads listed in this table are indeed no connects, but are represented in the boundary scan register by a ?place holder?. place holder registers are internally connected to v ss . 3. in boundary scan mode, differential input k and k are referenced to each other and must be at opposite logic levels for reliable operation. 4. zz must remain at v il during boundary scan. 5. in boundary scan mode, zq must be driven to v ddq or v ss supply rail to ensure consistent results.
hm62l36256 series 19 6. m1 and m2 must be driven to v dd , v ddq or v ss supply rail to ensure consistent results. id register part revision number (31:28) device density and configuration (27:18) vendor definition (17:12) vendor jedec code (11:1) start bit (0) hm62l36256 0011 0011000100 00000000111 1 tap controller state diagram test-logic- reset run-test/ idle 1 0 0 update-dr 0 select- dr-scan capture-dr 0 0 1 0 1 1 shift-dr exit1-dr pause-dr exit2-dr 0 0 1 0 select- ir-scan capture-ir 0 0 1 0 1 1 shift-ir exit1-ir pause-ir exit2-ir 0 0 1 1 1 update-dr update-ir 1 0 1 0 1 1 1 notes: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck
hm62l36256 series 20 package outline hm62l36256bp series (bp-119c) hitachi code jedec eiaj mass bp-119c 1.0 g unit: mm a 0.20 4 14.00 13.00 1.27 1.27 22.00 13.88 c c 0.35 0.30 119 0.88 0.06 cab m 0.15 c m c 0.20 a 1 2 3 4 5 6 7 b c d e f g h j k l m n p r t u y 0.69 0.08 2.02 0.22 (0.15) details of the part y b
hm62l36256 series 21 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi?s or any third party?s patent, copyright, trademark, o r other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party?s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest produ ct standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi?s sale s office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bea rs no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damag e due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi?s sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: (03) 3270-2111 fax: (03) 3270-5109 copyright ? hitachi, ltd., 2001. all rights reserved. printed in japan. hitachi asia ltd. hitachi tower 16 collyer quay #20-00 singapore 049318 tel : <65>-538-6533/538-8577 fax : <65>-538-6933/538-3877 url : http://semiconductor.hitachi.com.sg url http://www.hitachisemiconductor.com/ hitachi asia ltd. (taipei branch office) 4/f, no. 167, tun hwa north road hung-kuo building taipei (105), taiwan tel : <886>-(2)-2718-3666 fax : <886>-(2)-2718-8180 telex : 23222 has-tp url : http://www.hitachi.com.tw hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel : <852>-(2)-735-9218 fax : <852>-(2)-730-0281 url : http://semiconductor.hitachi.com.hk hitachi europe gmbh electronic components group dornacher stra?e 3 d-85622 feldkirchen postfach 201, d-85619 feldkirchen germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi europe ltd. electronic components group whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 585200 hitachi semiconductor (america) inc. 179 east tasman drive san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to: colophon 5.0

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